The present invention is directed to integrated circuits and their processing for the manufacture of semiconductor devices. More particularly, the invention provides methods and structures for manufacturing planar bond pad structures for advanced integrated circuit devices, but it would be recognized that the invention has a much broader range of applicability.
Integrated circuits have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. Conventional integrated circuits provide performance and complexity far beyond what was originally imagined. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry,” has become smaller with each generation of integrated circuits.
Increasing circuit density has not only improved the complexity and performance of integrated circuits but has also provided lower cost parts to the consumer. An integrated circuit or chip fabrication facility can cost hundreds of millions, or even billions, of U.S. dollars. Each fabrication facility will have a certain throughput of wafers, and each wafer will have a certain number of integrated circuits on it. Therefore, by making the individual devices of an integrated circuit smaller, more devices may be fabricated on each wafer, thus increasing the output of the fabrication facility. Making devices smaller is very challenging, as each process used in integrated fabrication has a limit. That is to say, a given process typically only works down to a certain feature size, and then either the process or the device layout needs to be changed. Additionally, as devices require faster and faster designs, process limitations exist with certain conventional processes and materials.
An example of such a process is the manufacture of bonding pad structures of integrated circuit devices. Such bonding pad structures have traditionally became smaller and smaller and occupy a smaller region of silicon real estate. Although there have been significant improvements, designs for bond pad structures still have many limitations. As merely an example, these designs must become smaller but still provide sufficient mechanical properties to support a bonded wire structure. Conventional bonding pad designs often have quality and reliability problems in fine pitch designs due to non-planar bonding surfaces. As illustrated in FIG. 1, a conventional bond pad structure 100 includes a passivation layer 102 that is elevated over a portion of metal layer 104. An elevated portion of passivation layer 102 is needed to seal the underlying metal layer region 104. Unfortunately, the elevation in passivation layer 102 results in a nonuniform surface 106, or crown, for bump termination electrode 108. In another conventional bonding pad structure 200, crown formation on surface 206 is precluded by avoiding areas directly overlying the periphery of metal layer region 204 (or corresponding to the elevated portions of passivation layer 202). However, this structure impairs bondability by reducing the total surface area available for bonding. Additionally, conventional bonding pad designs often require complex manufacturing processes, such two masks processes or elevated passivation layers. These and other limitations will be described in further detail throughout the present specification and more particularly below.
From the above, it is seen that an improved technique for processing semiconductor devices is desired.